Sdc timing constraints, Sdc timing constraints -34 – Altera Transceiver PHY IP Core User Manual
Page 409
Name
Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
rx_std_prbs_err
Output Yes
When asserted, indicates an error only
after the
rx_std_prbs_done
signal has
been asserted. This signal pulses for every
error that occurs. Errors can only occur
once per word.
To clear the PRBS pattern and deassert the
rx_std_prbs_done
signal by writing to the
memory-mapped register
PRBS Error
Clear
that you access through the
Transceiver Reconfiguration Controller IP
Core.
Miscellaneous
tx_std_elecidle[
Input
When asserted, enables a circuit to detect a
downstream receiver. This signal must be
driven low when not in use because it
causes the TX PMA to enter electrical idle
mode with the TX serial data signals in
tristate mode.
rx_std_signaldetect[
1:0]
Output No
Signal threshold detect indicator. When
asserted, it indicates that the signal present
at the receiver input buffer is above the
programmed signal detection threshold
value. You must synchronize this signal.
Related Information
SDC Timing Constraints
This section describes SDC timing constraints.
The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS and 10G
PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures.
You may choose one of the following three approaches to identify these false timing paths to the
Quartus II or TimeQuest software.
• You can cut these paths in your Synopsys Design Constraints (.sdc) file by using the
set_false_path
command as shown in the following example.
13-34
SDC Timing Constraints
UG-01080
2015.01.19
Altera Corporation
Arria V Transceiver Native PHY IP Core