Altera Transceiver PHY IP Core User Manual
Page 278
Serial Data Rate (Mbps)
Channel Width (FPGA-PCS Fabric)
Single-Width
Double-Width
8-Bit
16-Bit
16-Bit
32-Bit
1228.8
Yes
Yes
Yes
Yes
2457.6
No
Yes
Yes
Yes
3072
No
Yes
Yes
Yes
4915.2
No
No
No
Yes
6144
No
No
No
Yes
Additional Options Parameters for Deterministic Latency PHY
This section describes the settings available on the Additional Options tab for the Deterministic Latency
PHY IP core.
Name
Value
Description
Word alignment mode
The word aligner restores word boundaries of
received data based on a predefined alignment
pattern. The word aligner automatically performs an
initial alignment to the specified word pattern after
reset deassertion. You can select 1 of the following 2
modes: Deterministic latency state machine or
Manual
11-10
Additional Options Parameters for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation
Deterministic Latency PHY IP Core
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)