Altera Transceiver PHY IP Core - Manual (Page 285)

Table 11-9: Avalon-ST TX Interface
The following table describes the signals in the Avalon-ST input interface. These signals are driven from the MAC
to the PCS. This is an Avalon sink interface.
Signal Name Direction Description
tx_parallel_data[()-
1:0]
Input This is TX parallel data driven from the MAC. The
ready latency on this interface is 0, so that the PHY must
be able to accept data as soon as it comes out of reset.
Refer to for definitions of the control and status signals
with 8B/10B encoding enabled and disabled. Refer to
Table 11-11 for the signals that correspond to data,
control, and status signals.
tx_clkout[-:0]
Output This is the clock for TX parallel data, control, and status
signals.
tx_datak[(/)-1:0]
Input Data and control indicator for the transmitted data.
When 0, indicates that
tx_parallel_data
is data, when
1, indicates that
tx_parallel_data
is control.
Table 11-10: Signal Definitions for tx_parallel_data with and without 8B/10B Encoding
The following table shows the signals within tx_parallel_data that correspond to data, control, and status signals.
TX Data Word Description
Signal Definitions with 8B/10B Enabled
tx_parallel_data[7:0]
TX data bus
tx_parallel_data[8]
TX data control character
tx_parallel_data[9]
Force disparity, validates disparity field.
tx_parallel_data[10]
Specifies the current disparity as follows:
• 1'b0 = positive
• 1'b1 = negative
Signal Definitions with 8B/10B Disabled
tx_parallel_data[9:0]
TX data bus
tx_parallel_data[10]
Unused
UG-01080
2015.01.19
Data Interfaces for Deterministic Latency PHY 11-17
Deterministic Latency PHY IP Core Altera Corporation
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