Altera Transceiver PHY IP Core - Manual (Page 505)

Parameter Range Description
Enable rx_std_signaldetect port On/Off When you turn this option On, the
optional
rx_std_signaldetect
output
port is enabled. This signal is required
for the PCI Express protocol. If
enabled, the signal threshold detection
circuitry senses whether the signal level
present at the RX input buffer is above
the signal detect threshold voltage that
you specified.
For SATA / SAS applications, enable
this port and set the following QSF
assignments to the transceiver receiver
pin:
•
set_instance_assignment -name
XCVR_RX_SD_ENABLE ON
•
set_instance_assignment -name
XCVR_RX_SD_THRESHOLD 7
•
set_instance_assignment -name
XCVR_RX_COMMON_MODE_VOLTAGE
VTT_OP55V
•
set_instance_assignment -name
XCVR_RX_SD_OFF 1
•
set_instance_assignment -name
XCVR_RX_SD_ON 2
Interfaces
The Native PHY includes several interfaces that are common to all parameterizations.
The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.
The Native PHY uses the following prefixes for port names:
• Standard PCS ports—
tx_std
,
rx_std
The port descriptions use the following variables to represent parameters:
• <n>—The number of lanes
• <p>—The number of PLLs
• <r>—The number of CDR references clocks selected
Common Interface Ports
Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel
data ports, and reconfig interface ports.
15-22 Interfaces
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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