Altera Transceiver PHY IP Core - Manual (Page 587)

Signal Name Direction Clock Domain Description
rx_digital-
reset[ -1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Digital reset for RX. The width of this signal
depends on the number of channels. This signal
is asserted when any of the following
conditions is true:
•
reset
is asserted
•
rx_analogreset
is asserted
•
rx_cal_busy
is asserted
•
rx_is_lockedtodata
is deasserted and
rx_
manual
is deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
rx_digitalreset
.
rx_analogreset
[-1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Analog reset for RX. When asserted, resets the
RX CDR and the RX PMA blocks of the
transceiver PHY. This signal is asserted when
any of the following conditions is true:
•
reset
is asserted
•
rx_cal_busy
is asserted
The width of this signal depends on the number
of channels.
rx_ready[-1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Status signal to indicate when the RX reset
sequence is complete. This signal is deasserted
while the RX reset is active. It is asserted a few
clock cycles after the deassertion of
rx_
digitalreset
. Some protocol implementa‐
tions may require you to monitor this signal
prior to sending data. The width of this signal
depends on the number of RX channels.
pll_powerdown[
-
1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Asserted to power down a transceiver PLL
circuit. When asserted, the selected TX PLL is
reset.
Timing Constraints for Bonded PCS and PMA Channels
For designs that use bonded TX PCS and PMA channels, the digital reset signal to all TX channels within
a bonded group must meet a maximum skew tolerance imposed by physical routing. This skew tolerance
is one-half the TX parallel clock cycle (
tx_clkout
). This requirement is not necessary for bonded TX
PMA-only channels or for RX PCS channels.
17-10 Timing Constraints for Bonded PCS and PMA Channels
UG-01080
2015.01.19
Altera Corporation Transceiver PHY Reset Controller IP Core
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