Altera Transceiver PHY IP Core User Manual
Page 307
RX CDR Options
Table 12-6: RX PMA Parameters
The following table describes the RX CDR options you can specify. For more information about the CDR
circuitry, refer to the Receiver Clock Data Recovery Unit section in Clock Networks and PLLs in Stratix V
Devices.
Parameter
Range
Description
Enable CDR dynamic
reconfiguration
On/Off
When you turn this option On, you can dynamically
change the reference clock input the CDR circuit.
This option is also required to simulate TX PLL
reconfiguration.
Number of CDR reference
clocks
1-5
Specifies the number of reference clocks for the
CDRs.
Selected CDR reference clock
0-4
Specifies the index of the selected CDR reference
clock.
Selected CDR reference clock
frequency
Device Dependent Specifies the frequency of the clock input to the CDR.
PPM detector threshold
+/- 1000 PPM
Specifies the maximum PPM difference the CDR can
tolerate between the input reference clock and the
recovered clock.
Enable rx_is_lockedtodata
port
On/Off
When you turn this option On, the
rx_is_lockedto-
data
port is an output of the PMA.
Enable rx_is_lockedtoref
port
On/Off
When you turn this option On, the
rx_is_
lockedtoref
port is an output of the PMA.
Enable rx_set_locktodata
and rx_set_locktoref ports
On/Off
When you turn this option On, the
rx_set_
locktodata
and
rx_set_locktoref
ports are
outputs of the PMA.
Enable rx_pma_bitslip_port
On/Off
When you turn this option On, the
rx_pma_bitslip
is an input to the core. The deserializer slips one clock
edge each time this signal is asserted. You can use this
feature to minimize uncertainty in the serialization
process as required by protocols that require a
datapath with deterministic latency such as CPRI.
Enable rx_seriallpbken port
On/Off
When you turn this option On, the
rx_seriallpbken
is an input to the core. When your drive a 1 on this
input port, the PMA operates in loopback mode with
TX data looped back to the RX channel.
UG-01080
2015.01.19
PMA Parameters for Stratix V Native PHY
12-9
Stratix V Transceiver Native PHY IP Core
Altera Corporation