Altera Transceiver PHY IP Core User Manual
Page 688
Date
Document
Version
Changes Made
PHY IP Core for PCI Express (PIPE)
June 2012
1.7
• Added the following QSF settings to all transceiver PHY:
XCVR_
TX_PRE_EMP_PRE_TAP_USER
,
XCVR_TX_PRE_EMP_2ND_POST_TAP_
USER
, and 11 new settings for GT transceivers.
• Added reference Stratix V Transceiver Architecture chapter for
detailed explanation of PCS blocks.
• Changed the default value for
XCVR_REFCLK_PIN_TERMINATION
from DC_coupling_internal_100_Ohm to AC_coupling.
• Corrected definition of
tx_bitslipboundary_select
register.
• Changed
pipe_rate
signal to 2 bits.
• Added the following restriction in the dynamic reconfiguration
section: three channels share an Avalon-MM slave interface
which must connect to the same Transceiver Reconfiguration
Controller IP Core.
Custom PHY IP Core
June 2012
1.7
• Added the following QSF settings to all transceiver PHY:
XCVR_
TX_PRE_EMP_PRE_TAP_USER
,
XCVR_TX_PRE_EMP_2ND_POST_TAP_
USER
, and 11 new settings for GT transceivers.
• Added reference to Stratix V Transceiver Architecture chapter
for detailed explanation of the PCS blocks.
• Updated definition of
rx_enapatternalign
: It is edge sensitive
in most cases; however, if the PMA-PCS interface width is 10
bits, it is level sensitive.
• Added definition for
rx_byteordflag
output status signal
which is created when you enable the byte ordering block.
• Changed the default value for
XCVR_REFCLK_PIN_TERMINATION
from DC_coupling_internal_100_Ohm to AC_coupling.
• Added arrows indicating Transceiver Reconfiguration
Controller IP Core connection to block diagram.
• Changed the maximum frequency of
phy_mgmt_clk
to 150 MHz
if the same clock is used for the Transceiver Reconfiguration
Controller IP Core.
• Added the following restriction in the dynamic reconfiguration
section: three channels share an Avalon-MM slave interface
which must connect to the same Transceiver Reconfiguration
Controller IP Core.
Low Latency PHY IP Core
21-28
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core