1g/10gbe phy register definitions, 1g/10gbe phy register definitions -15 – Altera Transceiver PHY IP Core User Manual
Page 124
Signal Name
Direction
Description
mgmt_write
Input
Write signal. Active high.
mgmt_read
Input
Read signal. Active high.
mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
Related Information
1G/10GbE PHY Register Definitions
You can access the 1G/10GbE registers using the Avalon-MM PHY management interface with word
addresses and a 32-bit embedded processor. A single address space provides access to all registers.
Notes:
• Unless otherwise indicated, the default value of all registers is 0.
• Writing to reserved or undefined register addresses may have undefined side effects.
• To avoid any unspecified bits to be erroneously overwritten, you must perform read-modify-writes to
change the register values.
Table 5-13: 1G/10GbE Register Definitions
Addr
Bit
R/W
Name
Description
0xB0
0
RW
Reset SEQ
When set to 1, resets the sequencer. This bit must
be used in conjunction with SEQ Force
Mode[2:0] . This reset self clears.
1
Reserved.
2
RW
Disable LF Timer
When set to 1, disables the Link Fault timer.
When set to 0, the Link Fault timer is enabled.
6:4
RW
SEQ Force Mode[2:0]
Forces the sequencer to a specific protocol.
Allows you to change speeds if you have turned
on Enable automatic speed detection in the GUI.
You must write the Reset SEQ bit to 1 for the
Force to take effect. The following encodings are
defined:
• 3'b000: No force
• 3'b001: GigE
• 3'b010: Reserved
• 3'b011: Reserved
• 3'b100: 10GBASE-R
• 3'b101: Reserved
• Others: Reserved
UG-01080
2015.01.19
1G/10GbE PHY Register Definitions
5-15
1G/10 Gbps Ethernet PHY IP Core
Altera Corporation