Transceiver phy reset controller ip core, Transceiver phy reset controller ip core -1 – Altera Transceiver PHY IP Core User Manual
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Transceiver PHY Reset Controller IP Core
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2015.01.19
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The Transceiver PHY Reset Controller IP Core is a highly configurable core that you can use to reset
transceivers in Arria V, Arria V GZ, Cyclone V, or Stratix V devices. This reset controller is an alternate
controller that you can use instead of the embedded reset controller for the Custom, Low Latency, and
Deterministic Latency PHY IP cores. And, you can use it to reset the Stratix V, Arria V, Arria V GZ, and
Cyclone V Native Transceiver PHYs which do not include imbedded reset controllers. You can use it to
specify a custom reset sequence. You can also modify the clear text Verilog HDL file provided to
implement custom reset logic. The Reset Controller handles all reset sequencing of the transceiver to
enable successful operation. It provides the functionality of the embedded reset controller and the
following additional options:
• Separate or shared reset controls per channel
• Separate controls for the TX and RX channels and PLLs
• Synchronization of the reset inputs
• Hysteresis for PLL locked status inputs
• Configurable reset timings
• Automatic or manual reset recovery mode
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