Altera Transceiver PHY IP Core User Manual
Page 205
Signal Name
Direction
Description
phy_mgmt_write
Input
Write signal.
phy_mgmt_read
Input
Read signal.
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write request.
When asserted, control signals to the Avalon-MM slave
interface must remain constant.
PHY for PCIe (PIPE) Register Interface and Register Descriptions
on page 8-15 describes the registers
that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit
embedded processor. A single address space provides access to all registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 8-11: PCI Express PHY (PIPE) IP Core Registers
Word Addr
Bits
R/W
Register Name
Description
PMA Common Control and Status Registers
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX CMU PLL (P)
is locked to the input reference clock. There
is typically one
pma_tx_pll_is_locked
bit
per system.
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW
reset_ch_bitmask
Reset controller channel bitmask for digital
resets. The default value is all 1s. Channel
<n> can be reset when
bit<n> = 1.
0x042 [1:0]
W
reset_control
(write)
Writing a 1 to bit 0 initiates a TX digital
reset using the reset controller module. The
reset affects channels enabled in the
reset_
ch_bitmask
. Writing a 1 to bit 1 initiates a
RX digital reset of channels enabled in the
reset_ch_bitmask
.
Refer to Timing Constraints for Reset
Signals when Using Bonded PCS Channels
for a SDC constraint you must include in
your design.
R
reset_status
(read)
Reading bit 0 returns the status of the reset
controller TX ready bit. Reading bit 1
returns the status of the reset controller RX
ready bit.
Reset Controls –Manual Mode
UG-01080
2015.01.19
PHY for PCIe (PIPE) Register Interface and Register Descriptions
8-17
PHY IP Core for PCI Express (PIPE)
Altera Corporation