Altera Transceiver PHY IP Core User Manual
Page 176
Signal Name
Direction
Description
multi-lane configurations, the
tx_datain_bp
signals must be logically Ored. The latency on this
Avalon-ST interface is 0 cycles. The Interlaken MAC
must only drive valid user data on
tx_parallel_
data
and
tx_parallel_data
data bus as soon as
tx_ready
and
tx_sync_done
are both asserted. The
tx_datain_bp
signal is
connected to the partial empty threshold of the TX
FIFO, so that when
tx_datain_bp
is deasserted
the TX FIFO back pressures the Interlaken MAC. Stop
sending TX data to the PHY when this signal is
deasserted.
The Interlaken MAC can continue driving data to the
TX FIFO when
tx_datain_bp
is asserted. The
Interlaken MAC should gate
tx_parallel_data
[65]
, which operates as a data_valid signal, based on
tx_datain_bp
. This output is synchronous to the
tx_coreclkin
clock domain. Or, you can also tie
tx_
datain_bp
directly to
tx_parallel_data
[65]
. For Quartus II releases prior to 12.0, you must
pre-fill the TX FIFO before
tx_sync_done
can be
asserted. Do not use valid data to pre-fill the TX FIFO.
Use the following Verilog HDL assignment for
Quartus II releases prior to 12.0:
assign tx_parallel_data[65] = (!tx_sync_
done)?1'b1:tx_datain_bp[0];
tx_clkout
Output
For single lane Interlaken links,
tx_user_clkout
is
available when you do not create the optional
tx_
coreclkin
. For Interlaken links with more than 1
lane,
tx_coreclkin
is required and
tx_user_clkout
cannot be used.
tx_coreclkin
must have a minimum
frequency of the lane data rate divided by 67. The
frequency range for
tx_coreclkin
is (data rate/40) -
(data rate/67). For best results, Altera recommends
that
tx_coreclkin
= (data rate/40).
tx_user_clkout
Output
For single lane Interlaken links,
tx_user_clkout
is
available when you do not create the optional
tx_
coreclkin
. For Interlaken links with more than 1
lane,
tx_coreclkin
is required and
tx_user_clkout
cannot be used. You can use a minimum frequency of
lane datarate divided by 67 for
tx_coreclkin
,
although Altera recommends that
tx_coreclkin
frequency of the lane data rate divided by 40 for best
performance.
UG-01080
2015.01.19
Interlaken PHY Avalon-ST TX Interface
7-9
Interlaken PHY IP Core
Altera Corporation