Altera Transceiver PHY IP Core User Manual
Page 74
• FEC Block Synchronizer: The FEC block synchronizer achieves FEC block delineation by locking to
correctly received FEC blocks. An algorithm with hysteresis maintains block and word delineation.
• FEC Descrambler: The FEC descrambler descrambles the received data to regenerate unscrambled
data utilizing the original FEC scrambler polynomial.
• FEC Decoder:The FEC decoder performs the (2112, 2080) decoding by analyzing the received FEC
block for errors. It can correct burst errors of 11 bits per FEC block. The FEC receive gearbox adapts
the data width to the larger bus width of the PCS channel. It supports a 64:65 ratio.
• FEC Transcode Decoder: The FEC transcode decoder performs 65-bit to 64B/66B reconstruction by
regenerating the 64B/66B sync header.
4-18
Forward Error Correction (Clause 74)
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
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