Phase compensation fifo, Phase compensation fifo -11 – Altera Transceiver PHY IP Core User Manual
Page 494
Parameter
Range
Description
Enable Standard PCS low latency
mode
On/Off
When you turn this option On, all PCS functions
are disabled except for the phase compensation
FIFO, byte serializer and byte deserializer. This
option creates the lowest latency Native PHY that
allows dynamic reconfigure between multiple
PCS datapaths.
Phase Compensation FIFO
The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating
for the clock phase difference between the low speed parallel clock and FPGA fabric interface clock.
Note: For more information refer to the Receiver Phase Compensation FIFO and Transmitter Phase
Compensation FIFO sections in the Transceiver Architecture in Cyclone V Devices.
Table 15-8: Phase Compensation FIFO Parameters
Parameter
Range
Description
TX FIFO mode
low_latency
register_fifo
The following 2 modes are possible:
• low_latency: This mode adds 3–4 cycles of
latency to the TX datapath.
• register_fifo: In this mode the FIFO is
replaced by registers to reduce the latency
through the PCS. Use this mode for
protocols that require deterministic
latency, such as CPRI.
RX FIFO mode
low_latency
register_fifo
The following 2 modes are possible:
• low_latency: This mode adds 2–3 cycles of
latency to the TX datapath.
• register_fifo: In this mode the FIFO is
replaced by registers to reduce the latency
through the PCS. Use this mode for
protocols that require deterministic
latency, such as CPRI.
Enable tx_std_pcfifo_full port
On/Off
When you turn this option On, the TX Phase
compensation FIFO outputs a FIFO full status
flag.
Enable tx_std_pcfifo_empty port
On/Off
When you turn this option On, the TX Phase
compensation FIFO outputs a FIFO empty
status flag.
UG-01080
2015.01.19
Phase Compensation FIFO
15-11
Cyclone V Transceiver Native PHY IP Core Overview
Altera Corporation