Altera Transceiver PHY IP Core - Manual (Page 461)

Name Direction Description
tx_pma_txdetectrx
Input When asserted, the RX detect block in the TX
PMA detects the presence of a receiver at the
other end of the channel. After receiving a
tx_
pma_txdetectrx
request, the receiver detect
block initiates the detection process. Only for
QPI applications.
tx_pma_rxfound
Output Indicates the status of an RX detection in the
TX PMA. Only for QPI applications.
rx_pma_qpipulldn
Input Control input port for Quick Path Interconnect
(QPI) applications. This is an active low signal.
When asserted, the receiver pulls the input
signal to low state. Use this port only for QPI
applications.
TX and RX Serial Ports
tx_serial_data
[ -1:0]
Output TX differential serial output data.
rx_serial_data
[ -1:0]
Input RX differential serial output data.
Control and Status Ports
rx_seriallpbken
[ -1:0]
Input When asserted, the transceiver enters loopback
mode. Loopback drives TX data to the RX
interface.
rx_set_locktodata
[ -1:0]
Input When asserted, programs the RX CDR to
manual lock to data mode in which you control
the reset sequence using the
rx_setlocktoref
and
rx_setlocktodata
. Refer to Reset
Sequence for CDR in Manual Lock Mode in
Transceiver Reset Control in Arria V GZ Devices
for more information about manual control of
the reset sequence.
rx_set_locktoref
[ -1:0]
Input When asserted, programs the RX CDR to
manual lock to reference mode in which you
control the reset sequence using the
rx_
setlocktoref
and
rx_setlocktodata
. Refer
to Reset Sequence for CDR in Manual Lock
Mode in Transceiver Reset Control in Arria V
GZ Devices for more information about manual
control of the reset sequence.
pll_locked
[
-1:0]
Output When asserted, indicates that the PLL is locked
to the input reference clock.
rx_is_lockedtodata
[ -1:0]
Output When asserted, the CDR is locked to the
incoming data.
14-50 Common Interface Ports for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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