Altera Transceiver PHY IP Core - Manual (Page 658)

ALTGX Parameter Name (Default Value) Custom PHY Parameter Name
What is the deserializer block width?
Single
Double Deserializer block width: (22)
Auto
Single
Double
Additional Options
Not available
Enable TX Bitslip
Create rx_coreclkin port
Create tx_coreclkin port
Create rx_recovered_clk port
Create optional ports
Avalon data interfaces
Force manual reset control
Protocol Settings-Word Aligner Word Aligner
Use manual word alignment mode
Use manual bitslipping mode
Use the built-in 'synchronization state
machine'
Word alignment mode
Enable run length violation checking with a
run length of
Run length
What is the word alignment pattern Word alignment pattern
What is the word alignment pattern length Word aligner pattern length
Protocol Settings-Rate match/Byte order Rate Match
What is the 20-bit rate match pattern1
(usually used for +ve disparity pattern)
Rate match insertion/deletion +ve disparity pattern
What is the 20-bit rate match pattern1
(usually used for -ve disparity pattern)
Rate match insertion/deletion -ve disparity pattern
Protocol Settings—Rate match/Byte order Byte Order
What is the byte ordering pattern Byte ordering pattern
(22) This parameter is on the Datapath tab.
20-12 Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices
UG-01080
2013.12.20
Altera Corporation Migrating from Stratix IV to Stratix V Devices Overview
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