Altera Transceiver PHY IP Core - Manual (Page 610)

Options
• Auto
• Low
• Medium
• High
Assign To
PLL instance
reserved_channel
Pin Planner and Assignment Editor Name
Parameter (Assignment Editor Only)
Description
Allows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express
(PIPE), you can use this QSF assignment in conjunction with the
master_ch_number
assignment to
specify channel 4 as the master channel. Available for Gen1, Gen2, and Gen3 variants.
Example: set_parameter -name reserved_channel true
-to ".pcie_i|altera_xcvr_pipe:
_inst|sv_xcvr_pipe_nr:pipe_nr_inst|sv_xcvr_pipe_native:
transceiver_core"
Options
TRUE
Assign To
Include in .qsf file
Related Information
Transceiver Configurations in Arria V GZ Devices
Refer to Advance [SIC] Channel Placement Guidelines for PIPE Configurations in this document.
XCVR_ANALOG_SETTINGS_PROTOCOL
Pin Planner and Assignment Editor Name
Transceiver Analog Settings Protocol
Description
Specifies the protocol that a transceiver implements. When you use this setting for fully characterized
devices, the Quartus II software automatically sets the optimal values for analog settings, including the
V
OD
, pre-emphasis, and slew rate. For devices that are not fully characterized, the Quartus II software
specifies these settings using preliminary data. If you assign a value to
XCVR_ANALOG_SETTINGS_PROTOCOL
,
you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the
19-16 reserved_channel
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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