Altera Transceiver PHY IP Core User Manual
Page 701
Date
Document
Version
Changes Made
December 2010
1.1
• Added simulation support in ModelSim SE
• Added PIPE low latency configuration option
• Changed
phy_mgmt_address
from 16 to 9 bits.
• Changed register map to show word addresses instead of a byte
offset from a base address.
• Added
tx_ready
,
rx_ready
,
pipe_txswing
, and
pipe_
rxeleciidle
signals
• Added
rx_errdetect
,
rx_disperr
, and
rx_a1a2sizeout
register fields
Custom PHY Transceiver
December 2010
1.1
• Added support for 8B/10B encoding and decoding in Stratix V
devices
• Added support for rate matching in Stratix V devices.
• Added support for Arria II GX, Arria II GZ, HardCopy IV GX,
and Stratix IV GX devices
• Changed
phy_mgmt_address
from 8 to 9 bits.
• Added many optional status ports and renamed some signals.
Refer to Figure 9–2 on page 9–15 and subsequent signal descrip‐
tions.
• Changed register map to show word addresses instead of a byte
offset from a base address.
Low Latency PHY IP Core
December 2010
1.1
• Renamed management interface, adding
phy_
prefix
• Changed
phy_mgmt_address
from 16 to 9 bits.
• Changed register map to show word addresses instead of a byte
offset from a base address.
• Removed
rx_offset_cancellation_done
signal. Internal reset
logic determines when offset cancellation has completed.
• Removed support for Stratix IV GX devices.
Transceiver Reconfiguration Controller
December 2010
1.1
• Reconfiguration is now integrated into the XAUI PHY IP Core
and 10GBASE-R PHY IP Core.
• Revised register map to show word addresses instead of a byte
offset from a base address.
Migrating from Stratix IV to Stratix V
December 2010
1.1
• Changed phy_mgmt_address from 16 to 9 bits.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-41
Additional Information for the Transceiver PHY IP Core
Altera Corporation