Altera Transceiver PHY IP Core - Manual (Page 371)

You can use the
tx_clkout
from any channel to transfer data, control, and status signals between the
FPGA fabric and the transceiver channels. Using the
tx_clkout
from the central channel results in
overall lower clock skew across lanes. In the FPGA fabric, you can drive the
tx_clkout
from the
connected channel to all other channels in the bonded group. For bonded clocking, connecting more than
one
tx_clkout
from the transceiver channel to the FPGA fabric results in a Fitter error. You can also
choose the
tx_pll_refclk
to transfer data, control, and status signals between the FPGA fabric and the
transceiver channels. Because this reference clock is also the input to the TX PLL, it has the required 0
ppm difference with respect to
tx_clkout
.
ATX, CMU and Fractional PLLs
For data rates above 8 Gbps, Altera recommends the ATX PLL because it has better jitter performance.
Refer to "Clock Network Maximum Data Rate Transmitter Specifications" in the Stratix V Device
Datasheet for detailed information about maximum data rates for the three different PLLs. The supported
data rates are somewhat higher when a design specifies up to 7 contiguous channels above and below the
ATX PLL rather than the maximum of 13 contiguous channels above and below the ATX PLL.
You can also use the CMU or fractional PLLs at lower data rates. If you select the CMU PLL as the TX
PLL it must be placed in physical channel 1 or 4 of the transceiver bank. That channel is not available as
an RX channel because the CMU PLL is not available to recover the clock from received data.
Consequently, the using the CMU PLL creates a gap in the contiguous channels.
Related Information
• Stratix V Device Datasheet
• Transceiver Clocking in Stratix V Devices
xN Non-Bonded Clocking
Non-bonded clocking routes only the high-speed serial clock from the TX PLL to the transmitter
channels. The local clock divider of each channel generates the low-speed parallel clock. Non-bonded
channels support dynamic reconfiguration of the transceiver.
xN non-bonded clocking has the following advantages:
• Supports data rate negotiation between link partners on a per-channel basis.
• Supports data rates are not simple integer multiples of a single base data rate.
• Supports PLL and channel reconfiguration.
The Native PHY preset for CPRI specifies non-bonded clocks. In multi-channel configurations, CPRI can
use both ATX PLLs in a transceiver bank to generate two base data rates. When necessary, CPRI uses
dynamic reconfiguration to change the local clock dividers to generate the negotiated clock rate.
The channel span for xN non-bonded clocks is almost identical to the span for bonded clocks as
illustrated in Figure 12-9 . However, the center channel that provides central clock divider cannot be used
as a data channel because this channel cannot generate the parallel clock. The maximum channel span is
26 channels. There is a single-channel break in the contiguous channel sequence.
Related Information
Transceiver Clocking in Stratix V Devices
UG-01080
2015.01.19
xN Non-Bonded Clocking 12-73
Stratix V Transceiver Native PHY IP Core Altera Corporation
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