Interlaken phy ip core, Interlaken phy ip core -1, Interlaken phy ip core fpga fabric – Altera Transceiver PHY IP Core User Manual
Page 168
Interlaken PHY IP Core
7
2015.01.19
UG-01080
The Altera Interlaken PHY IP Core implements Interlaken Protocol Specification, Rev 1.2.
Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. It supports
multiple instances, each with 1 to 24 lanes running at 10.3125 Gbps or greater in Arria V GZ and Stratix V
devices. The key advantages of Interlaken are scalability and its low I/O count compared to earlier
protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive
integrity checking. The Interlaken physical coding sublayer (PCS) transmits and receives Avalon-ST data
on its FPGA fabric interface. It transmits and receives high speed differential serial data using the PCML
I/O standard.
Figure 7-1: Interlaken PHY IP Core
P C S
PMA
Serializer
Framing:
Gearbox
Block Synchronization
64b/67b Encoding/Decoding
Scrambing/Descrambling
Lane-Based CRC32
DC Balancing
De-
Serializer
and CDR
HSSI I/O
Interlaken PHY IP Core
FPGA
Fabric
tx_serial_data
Avalon-ST
Tx and Rx
rx_serial_data
up to
14.1 Gbps
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Interface Specifications.
Interlaken operates on 64-bit data words and 3 control bits, which are striped round robin across the lanes
to reduce latency. Striping renders the interface independent of exact lane count. The protocol accepts
packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets
are split into small bursts which can optionally be interleaved. The burst semantics include integrity
checking and per channel flow control.
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