Altera Transceiver PHY IP Core User Manual
Page 336
Parameter
Range
Description
Enable rx_10g_frame_diag_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_diag_
err
output port. This signal is asserted
to indicate a diagnostic control word
error. This signal remains asserted
during the loss of block_lock and does
update until block_lock is recovered.
Enable rx_10g_frame_diag_status port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_diag_
status
2-bit output port per channel.
This port contains the lane Status
Message from the framing layer
Diagnostic Word, bits[33:32]. This
message is inserted into the next
Diagnostic Word generated by the
frame generation block.
Interlaken CRC32 Generator and Checker
CRC-32 provides a diagnostic tool on a per-lane basis. You can use CRC-32 to trace interface errors back
to an individual lane. The CRC-32 calculation covers the whole metaframe including the Diagnostic
Word itself. This CRC code value is stored in the CRC32 field of the Diagnostic Word. The following
table describes the CRC-32 parameters.
Table 12-28: Interlaken CRC32 Generator and Checker Parameters
Parameter
Range
Description
Enable Interlaken TX CRC32 Generator
On/Off
When you turn this option On, the TX
10G PCS datapath includes the CRC32
function.
Enable Interlaken RX CRC32 Generator
On/Off
When you turn this option On, the RX
10G PCS datapath includes the CRC32
function.
Enable rx_10g_crc32_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_crc32_err
port. This signal is asserted to indicate
that the CRC checker has found an error
in the current metaframe.
10GBASE-R BER Checker
The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE
802.3-2008 Clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid
synchronization headers within a 125-us period. If more than 16 invalid synchronization headers are
observed in a 125-us period, the BER monitor provides the status signal to the FPGA fabric, indicating a
high bit error. The following table describes the 10GBASE-R BER checker parameters.
12-38
10G PCS Parameters for Stratix V Native PHY
UG-01080
2015.01.19
Altera Corporation
Stratix V Transceiver Native PHY IP Core