Altera Transceiver PHY IP Core - Manual (Page 497)

Related Information
Transceiver Architecture in Cyclone V Devices
Byte Serializer and Deserializer
The byte serializer and deserializer allow the PCS to operate at twice the data width of the PMA serializer.
This feature allows the PCS to run at a lower frequency and accommodate a wider range of FPGA
interface widths.
Note: For more information refer to the Byte Serializer and Byte Deserializer sections in the Transceiver
Architecture in Cyclone V Devices.
Table 15-10: Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte serializer On/Off When you turn this option On, the PCS
includes a TX byte serializer which allows the
PCS to run at a lower clock frequency to
accommodate a wider range of FPGA interface
widths.
Enable RX byte deserializer On/Off When you turn this option On, the PCS
includes an RX byte deserializer which allows
the PCS to run at a lower clock frequency to
accommodate a wider range of FPGA interface
widths.
Related Information
Transceiver Architecture in Cyclone V Devices
8B/10B
The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. The
8B/10B decoder decodes the data into an 8-bit data and 1-bit control identifier.
In 8-bit width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or
data word) with proper disparity.
Note: For more information refer to the 8B/10B Encoder and 8B/10B Decoder sections in the Transceiver
Architecture in Cyclone V Devices.
Table 15-11: 8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B encoder On/Off When you turn this option On, the PCS includes
the 8B/10B encoder.
15-14 Byte Serializer and Deserializer
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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