Altera Transceiver PHY IP Core - Manual (Page 238)

Signal Name Direction Signal Name
rx_errdetect[(/)-1:0]
Output When asserted, indicates that a
received 10-bit code group has an 8B/
10B code violation or disparity error.
rx_syncstatus[ (/)-
1:0]
Output Indicates presence or absence of
synchronization on the RX interface.
Asserted when word aligner identifies
the word alignment pattern or
synchronization code groups in the
received data stream. This signal is
optional.
rx_is_lockedtoref[ -1:0]
Output Asserted when the receiver CDR is
locked to the input reference clock.
This signal is asynchronous. This
signal is optional.
rx_is_lockedtodata[ -1:0]
Output When asserted, the receiver CDR is in
to lock-to-data mode. When
deasserted, the receiver CDR lock
mode depends on the
rx_locktor-
efclk
signal level. This signal is
optional.
rx_signaldetect[ -1:0]
Output Signal threshold detect indicator
required for the PCI Express
protocol. When asserted, it indicates
that the signal present at the receiver
input buffer is above the
programmed signal detection
threshold value.
rx_bitslip[ -1:0]
Input Used for manual control of bit
slipping. The word aligner slips a bit
of the current word for every rising
edge of this signal. This is an
asynchronous input signal and inside
there is a synchronizer to synchronize
it with
rx_pma_clk/rx_clkout
.
rx_bitslipboundaryselectout
[ 5-1:0]
Output This signal is used for bit slip word
alignment mode. It reports the
number of bits that the RX block
slipped to achieve a deterministic
latency.
rx_patterndetect[(/)-
1:0]
Output When asserted, indicates that the
programmed word alignment pattern
has been detected in the current word
boundary.
UG-01080
2015.01.19
Optional Status Interface 9-25
Custom PHY IP Core Altera Corporation
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