Altera Transceiver PHY IP Core User Manual
Page 392
Table 13-16: Status Flag Mappings for Simplified Native PHY Interface
Status Condition
Protocol
Mapping of Status Flags to RX Data
Value
Full
PHY IP Core for PCI
Express (PIPE)
Basic double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
XAUI, GigE, Serial RapidIO
double width
rx_std_rm_fifo_full
1'b1 = full
All other protocols
Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
2'b11 = full
Empty
PHY IP Core for PCI
Express (PIPE)
Basic double width
RXD[62:62] = rx_
rmfifostatus[1:0]
, or
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[30:29] = rx_
rmfifostatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
(2'b10 AND (PAD
OR EDB) = empty)
(13)
XAUI, GigE, Serial RapidIO
double width
rx_std_rm_fifo_empty
1'b1 = empty
All other protocols
Depending on the FPGA fabric to
PCS interface width either:
RXD[46:45] = rx_rmfifos-
tatus[1:0]
, or
RXD[14:13] = rx_rmfifos-
tatus[1:0]
(2'b10 AND (PAD
OR EDB) = empty)
(13)
PAD and EBD are control characters. PAD character is typically used fo fill in the remaining lanes in a
multi-lane link when one of the link goes to logical idle state. EDB indicates End Bad Packet.
UG-01080
2015.01.19
Rate Match FIFO
13-17
Arria V Transceiver Native PHY IP Core
Altera Corporation