Low latency phy ip core, Low latency phy ip core -1 – Altera Transceiver PHY IP Core User Manual
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Low Latency PHY IP Core
10
2015.01.19
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The Altera Low Latency PHY IP Core receives and transmits differential serial data, recovering the RX
clock from the RX input stream. The PMA connects to a simplified PCS, which contains a phase
compensation FIFO. Depending on the configuration you choose, the Low Latency PHY IP Core instanti‐
ates one of the following channels:
• GX channels using the Standard PCS
• GX channels using the 10G PCS
• GT channels in PMA Direct mode
An Avalon-MM interface provides access to control and status information. The following figure
illustrates the top-level modules of the Low Latency PHY IP Core.
Figure 10-1: Low Latency PHY IP Core-Stratix V Devices
10GBASE-R PHY IP Core
10.3125 Gbps serial
XFI/SFP+
Stratix V FPGA
PMA
Hard PCS
10GBASE-R
64b/66b
Scrambler
Gearbox
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status
Transceiver
Reconfiguraiton
Because the Low Latency PHY IP Core bypasses much of the PCS, it minimizes the PCS latency.
For more detailed information about the Low Latency datapath and clocking, refer to the refer to the
“Stratix V GX Device Configurations” section in the Transceiver Configurations in Stratix V Devices
chapter of the Stratix V Device Handbook.
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