Altera Transceiver PHY IP Core User Manual
Page 532
Reconfig Addr
Bits
R/W
Register Name
Description
7’h0A
[9]
R
control and status
Error
. When asserted, indicates an error.
This bit is asserted if any of the following
conditions occur:
• The channel address is invalid.
• The PHY address is invalid.
• The PMA offset is invalid.
[8]
R
Busy
. When asserted, indicates that a
reconfiguration operation is in progress.
[1]
W
Read
. Writing a 1 to this bit triggers a read
operation.
[0]
W
Write
. Writing a 1 to this bit triggers a
write operation.
7’h0B
[5:0] RW
pma offset
Specifies the offset of the PMA analog
describes the valid offset values.
7’h0C
[6:0] RW
data
Reconfiguration data for the PMA analog
settings. Refer to
for valid
data values.
Refer to the Arria V Device Datasheet, the Cyclone V Device Datasheet, or the Stratix V Device Datasheet
for more information about the electrical characteristics of each device. The final values are currently
pending full characterization of the silicon.
Note: All undefined register bits are reserved.
Table 16-10: PMA Offsets and Values
Offset
Bits
R/W
Register Name
Description
0x0
[5:0]
RW
V
OD
VOD. The following encodings are
defined:
• 6’b000000:6’b111111:0–63
0x1
[4:0]
RW
Pre-emphasis pre-tap
The following encodings are defined:
• 5’b00000 and 5’b10000: 0
• 5’b00001–5’b01111: -15 to -1
• 5’b10001–5b’11111: 1 to 15
0x2
[4:0]
RW
Pre-emphasis first post-tap
The following encodings are defined:
• 5’b00000–5’b11111: 0–31
UG-01080
2015.01.19
Transceiver Reconfiguration Controller PMA Analog Control Registers
16-15
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation