Altera Transceiver PHY IP Core User Manual
Page 671
Chapter
Document
Version
Changes Made
Analog Parameters
Set Using QSF
Assignments
2.6
Made the following changes:
• Corrected values for
XCVR_REFCLK_PIN_TERMINATION
.
DC_
COUPLING_INTERNAL_100_OHM
should be
DC_COUPLING_
INTERNAL_100_OHMS
.
• Removed the options for
XCVR_TX_COMMON_MODE_VOLTAGE
and
XCVR_RX_COMMON_MODE_VOLTAGE
assignments and added a note
to use these assignments for Arria V, Arria V GZ, Cyclone V,
and Stratix V devices.
• Removed the options for
XCVR_GT_TX_COMMON_MODE_VOLTAGE
and
XCVR_GT_RX_COMMON_MODE_VOLTAGE
and added a note to
use these assigments for Stratix V GT devices.
Chapter
Document
Version
Changes Made
Introduction
2.5
Added information on running
ip-make-simscript
for designs
including multiple transceiver PHYs.
10GBASE-R PHY
2.5
Made the following changes:
• Corrected description of Table 3-2 Latency for TX and RX PCS
and PMA in Stratix V Devices. The FPGA fabric to PCS interface
width is 64 bits.
• Added the description for a new parameter - PCS / PMA
interface width in General Option Parameters section.
• Added frequency for
rx_recovered_clk[
. It's 257.8
MHz.
• Updated the descriptions of
rx_latency_adj_10g
and
tx_
latency_adj_10g
. Changed the width of these signals for all
references.
• Added description for Enable embedded reset controller
parameter General Option Parameters section.
• Added a new section Optional Reset Control and Status Interface.
Backplane Ethernet
10GBASE-KR PHY
2.5
Made the following changes:
• Updated the descriptions of
xgmii_tx_clk
and
xgmii_rx_clk
in
10GBASE-KR PHY Data Interfaces section.
• Updated the descriptions of
rx_latency_adj_1g
and
tx_
latency_adj_1g
. Changed the width of these signals for all
references.
• Added SDC Timing Constraints topic.
• Added parameter description for Use M20K for FEC Buffer (if
available).
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-11
Additional Information for the Transceiver PHY IP Core
Altera Corporation