Altera Transceiver PHY IP Core - Manual (Page 276)

Parameterizing the Deterministic Latency PHY
This section provides a list of steps on how to configure Deterministic Latency PHY
1. Under Tools > IP Catalog, select the device family of your choice.
2. Under Tools > IP Catalog > Interface Protocols > Transceiver PHY, select Deterministic Latency
PHY.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
a. Set the Deterministic Latency PHY general options parameters.
b. Set the Deterministic Latency PHY additional options parameters.
c. Set the Deterministic Latency PHY PLL reconfiguration parameters as required.
d. Set the Deterministic Latency PHY additional options parameters as required.
4. Click Finish.
Generates your customized Deterministic Latency PHY IP Core.
General Options Parameters for Deterministic Latency PHY
This section describes how to set basic parameters of your transceiver PHY for the Deterministic Latency
PHY IP core using the general options tab.
Use the General Options tab to set your basic device parameter settings.
Table 11-6: General Options
Name Value Description
Device family Arria V, Cyclone
V, Stratix V
Specifies the device family. Arria V, Cyclone V, and
Stratix V are available.
Mode of operation Duplex, TX, RX You can select to transmit data, receive data, or both.
Number of lanes 1-32 The total number of lanes in each direction.
FPGA fabric transceiver
interface width
8, 10, 16, 20, 32, 40 Specifies the word size between the FPGA fabric and
PCS. Refer to Table 11-7 for the data rates supported at
each word size.
PCS-PMA interface
width
10, 20 Specifies the datapath width between the transceiver PCS
and PMA. A deserializer in the PMA receives serial input
data from the RX buffer using the high-speed recovered
clock and deserializes it using the low-speed parallel
recovered clock.
PLL type CMU, ATX Specifies the PLL type. The CMU PLL has a larger
frequency range than the ATX PLL. The ATX PLL is
designed to improve jitter performance and achieves
lower channel-to-channel skew; however, it supports a
narrower range of data rates and reference clock
frequencies. Another advantage of the ATX PLL is that it
does not use a transceiver channel, while the CMU PLL
does. Because the CMU PLL is more versatile, it is
specified as the default setting.
11-8 Parameterizing the Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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