Altera Transceiver PHY IP Core - Manual (Page 395)

Parameter Range Description
Number of invalid words to lose
sync
1–256
Specifies the number of invalid data codes or
disparity errors that must be received before the
word aligner loses synchronization. The default
is 3.
Number of valid data words to
decrement error count
1–256
Specifies the number of valid data codes that
must be received to decrement the error
counter. If the word aligner receives enough
valid data codes to decrement the error count to
0, the word aligner returns to synchronization
lock.
Run length detector word count
0–63
Specifies the maximum number of contiguous
0s or 1s in the data stream before the word
aligner reports a run length violation.
Enable rx_std_wa_patternalign
port
On/Off Enables the optional
rx_std_wa_patternalign
control input port.
Enable rx_std_wa_a1a2size port On/Off Enables the optional
rx_std_wa_a1a2size
control input port.
Enable rx_std_bitslipboundarysel
port
On/Off Enables the optional
rx_std_wa_bitslipboun-
darysel
status output port.
Enable rx_std_bitslip port On/Off Enables the optional
rx_std_wa_bitslip
control input port.
Enable rx_std_runlength_err
port
On/Off Enables the optional
rx_std_wa_runlength_
err
control input port.
Related Information
Transceiver Architecture in Arria V Devices
Bit Reversal and Polarity Inversion
The bit reversal and polarity inversion functions allow you to reverse bit order, byte order, and polarity to
correct errors and to accommodate different layouts of data.
13-20 Bit Reversal and Polarity Inversion
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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