Altera Transceiver PHY IP Core User Manual
Page 252
Name
Value
Description
Bonding mode
×N
fb_compensation
Select ×N to use the same clock source for
up to 6 channels in a single transceiver bank,
resulting in reduced clock skew. You must
use contiguous channels when you select ×N
bonding. In addition, you must place logical
channel 0 in either physical channel 1 or 4.
Physical channels 1 and 4 are indirect
drivers of the ×N clock network.
Select fb_compensation (feedback
compensation) to use the same clock source
for multiple channels across different
transceiver banks to reduce clock skew.
For more information about bonding, refer
to “Bonded Channel Configurations Using
the PLL Feedback Compensation Path” in
Transceiver Clocking in Stratix V Devices in
volume 2 of the Stratix V Device Handbook.
FPGA fabric transceiver interface
width
8, 10, 16, 20, 32,
40,
50, 64, 66, 128
This option indicates the parallel data fabric
transceiver interface width. GT datapath
supports a single width of 128 bits. Refer to
Datapath Width Support for the
supported interface widths of the Standard
and 10G datapaths.
PCS PMA interface width
8, 10, 16, 20, 32,
30, 64
The PCS-PMA interface width depends on
the FPGA fabric transceiver interface
width and the Datapath type. Refer to
Datapath Width Support for the supported
interface widths of the Standard and 10G
datapaths.
PLL type
CMU
ATX
The CMU PLL is available for the Standard
and 10G datapaths. The ATX PLL is
available for the Standard, 10G, and GT
datapaths. The CMU PLL has a larger
frequency range than the ATX PLL. The
ATX PLL is designed to improve jitter
performance and achieves lower channel-to-
channel skew; however, it supports a
narrower range of data rates and reference
clock frequencies. Another advantage of the
ATX PLL is that it does not use a transceiver
channel, while the CMU PLL does.
An informational message displays in the
message panel if the PLL type that you select
is not available at the frequency specified.
UG-01080
2015.01.19
General Options Parameters
10-5
Low Latency PHY IP Core
Altera Corporation