Bit reversal and polarity inversion, Bit reversal and polarity inversion -20 – Altera Transceiver PHY IP Core User Manual
Page 503
Parameter
Range
Description
Enable rx_std_wa_patternalign
port
On/Off
Enables the optional
rx_std_wa_patternalign
control input port.
Enable rx_std_wa_a1a2size port
On/Off
Enables the optional
rx_std_wa_a1a2size
control input port.
Enable rx_std_bitslipboundarysel
port
On/Off
Enables the optional
rx_std_wa_bitslipboun-
darysel
status output port.
Enable rx_std_bitslip port
On/Off
Enables the optional
rx_std_wa_bitslip
control input port.
Enable rx_std_runlength_err
port
On/Off
Enables the optional
rx_std_wa_runlength_
err
control input port.
Related Information
Bit Reversal and Polarity Inversion
The bit reversal and polarity inversion functions allow you to reverse bit order, byte order, and polarity to
correct errors and to accommodate different layouts of data.
Table 15-15: Bit Reversal and Polarity Inversion Parameters
Parameter
Range
Description
Enable TX bit reversal
On/Off
When you turn this option On, the
word aligner reverses TX parallel data
before transmitting it to the PMA for
serialization. You can only change this
static setting using the Transceiver
Reconfiguration Controller.
Enable RX bit reversal
On/Off
When you turn this option On, the
rx_
std_bitrev_ena
port controls bit
reversal of the RX parallel data after it
passes from the PMA to the PCS.
Enable RX byte reversal
On/Off
When you turn this option On, the
word aligner reverses the byte order
before transmitting data. This function
allows you to reverse the order of bytes
that were erroneously swapped. The
PCS can swap the ordering of both 8
and10 bit words.
15-20
Bit Reversal and Polarity Inversion
UG-01080
2015.01.19
Altera Corporation
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