Altera Transceiver PHY IP Core - Manual (Page 117)

1G/10GbE PHY Clock and Reset Interfaces
This topic illustrates the 1G/10GbE PHY clock and reset connectivity and describes the clock and reset
signals.
Use the Transceiver PHY Reset Controller IP Core to automatically control the transceiver reset sequence.
This reset controller also has manual overrides for the TX and RX analog and digital circuits to allow you
to reset individual channels upon reconfiguration.
If you instantiate multiple channels within a transceiver bank they share TX PLLs. If a reset is applied to
this PLL, it will affect all channels. Altera recommends leaving the TX PLL free-running after the start-up
reset sequence is completed. After a channel is reconfigured you can simply reset the digital portions of
that specific channel instead of going through the entire reset sequence. If you are not using the sequencer
and the data link is lost, you must assert the
rx_digitalreset
when the link recovers. For more informa‐
tion about reset, refer to the "Transceiver PHY Reset IP Core" chapter in the Altera Transceiver PHY IP
Core User Guide.
Phy_mgmt_clk_reset
is the Avalon-MM reset signal.
Phy_mgmt_clk_reset
is also an input to the
Transceiver PHY Reset Controller IP Core which is a separately instantiated module not included in the
1G/10GbE and 10GBASE-KR variants. The Transceiver PHY Reset Controller IP Core resets the TX PLL
and RX analog circuits and the TX and RX digital circuits. When complete, the Reset Controller asserts
the
tx_ready
and
rx_ready
signals.
The following figure provides an overview of the clocking for this IP core.
Figure 5-3: Clocks for Standard and 10G PCS and TX PLLs
xgmii_rx_clk
156.25 MHz
xgmii_tx_clk
156.25 MHz
1G / 10G PHY
Stratix V STD
RX PCS
Stratix V
TX PMA tx_coreclkin_1g
125 MHz
Stratix V
RX PMA
TX PLL
TX PLL
40
rx_pld_clk rx_pma_clk
TX serial data
8 GMII TX Data
72 XGMII TX Data & Cntl
RX data
40 TX data
40
64
TX data
serial data
pll_ref_clk_10g
644.53125 MHz
or
322.265625 MHz
pll_ref_clk_1g
125 MHz
or
62.5 MHz
Stratix V STD
TX PCS
tx_pld_clk tx_pma_clk
8 GMII RX Data
pll_ref_clk_10g
72 72 XGMII RX Data & Cntl recovered clk
257.8125 MHz
161.1 MHz
rx_coreclkin_1g
125 MHz
Stratix V 10G
RX PCS
rx_pld_clk rx_pma_clk
Stratix V 10G
TX PCS
tx_pld_clk tx_pma_clk
fractional
PLL
(instantiate
separately)
GIGE
PCS
72
red = datapath includes FEC
GIGE
tx_clkout_1g
rx_clkout_1g
PCS
The following table describes the clock and reset signals.
5-8 1G/10GbE PHY Clock and Reset Interfaces
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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