Altera Transceiver PHY IP Core - Manual (Page 260)

Related Information
Analog Parameters Set Using QSF Assignments on page 19-1
Low Latency PHY Interfaces
The following figure illustrates the top-level signals of the Custom PHY IP Core. The variables in this
figure represent the following parameters:
• —The number of lanes
• —The width of the FPGA fabric to transceiver interface per lane
Figure 10-2: Top-Level Low Latency Signals
Low Latency PHY IP Core Top-Level Signals
tx_serial_data
rx_serial_data
rx_is_lockedtodata[ -1:0]
rx_is_lockedtoref[ -1:0]
pll_locked[ -1:0]
tx_bitslip
rx_bitslip
pll_powerdown
tx_digitalreset
tx_analogreset
tx_cal_busy
rx_digitalreset
rx_analogreset
rx_cal_busy
reconfig_to_xcvr[( 70-1):0]
reconfig_from_xcvr[( 46-1):0]
Control and
Status
(Optional)
tx_parallel_data[ -1:0]
tx_clkout[ -1:0]
rx_parallel_data[ -1:0]
rx_clkout[ -1:0]
tx_ready[ -1:0]
rx_ready[ -1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
tx_coreclkin[ -1:0]
rx_coreclkin[ -1:0]
Avalon-MM PHY
Management
Interface
Avalon-ST TX and RX
to and from MAC
Serial
Data
Dynamic
Reconfiguration
Reset Control
and Status
(Optional)
Clocks
Optional
Note: By default block diagram shown in the MegaWizard Plug-In Manager labels the external pins with
the interface type and places the interface name inside the box. The interface type and name are
used in the _hw.tcl file that describes the component. If you turn on Show signals, the block
diagram displays all toplevel signal names.
For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference
chapter in volume 1 of the Quartus II Handbook.
Low Latency PHY Data Interfaces
The following table describes the signals in the Avalon-ST interface. This interface drives AvalonST TX
and RX data to and from the FPGA fabric. These signals are named from the point of view of the MAC so
that the TX interface is an Avalon-ST sink interface and the RX interface is an Avalon-ST source.
UG-01080
2015.01.19
Low Latency PHY Interfaces 10-13
Low Latency PHY IP Core Altera Corporation
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