Altera Transceiver PHY IP Core - Manual (Page 599)

PLL_BANDWIDTH_PRESET
Pin Planner and Assignment Editor Name
PLL Bandwidth Preset
Description
Specifies the PLL bandwidth preset setting
Options
• Auto
• Low
• Medium
• High
Assign To
PLL instance
XCVR_RX_DC_GAIN
Pin Planner and Assignment Editor Name
Receiver Buffer DC Gain Control
Description
Controls the amount of a stage receive-buffer DC gain.
Options
0 –1
Assign To
Pin - RX serial data
XCVR_ANALOG_SETTINGS_PROTOCOL
Pin Planner and Assignment Editor Name
Transceiver Analog Settings Protocol
Description
Specifies the protocol that a transceiver implements. When you use this setting for fully characterized
devices, the Quartus II software automatically sets the optimal values for analog settings, including the
V
OD
, pre-emphasis, and slew rate. For devices that are not fully characterized, the Quartus II software
specifies these settings using preliminary data. If you assign a value to
XCVR_ANALOG_SETTINGS_PROTOCOL
,
you cannot assign a value for any settings that this parameter controls. For example, for PCIe, the
UG-01080
2015.01.19
PLL_BANDWIDTH_PRESET 19-5
Analog Parameters Set Using QSF Assignments Altera Corporation
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