Altera Transceiver PHY IP Core - Manual (Page 38)

Figure 3-6: 10GBASE-R PHY Top-Level Signals
xgmii_tx_dc[71:0]
tx_ready
xgmii_tx_clk
xgmii_rx_dc[71:0]
rx_ready
rx_data_ready[-1:0]
xgmii_rx_clk
rx_coreclkin
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
10GBASE-R Top-Level Signals
Dynamic
Reconfiguration
External
PMA Control
Stratix IV
Devices
rx_serial_data
tx_serial_data
gxb_pdn
pll_pdn
cal_blk_pdn
cal_blk_clk
pll_locked
reconfig_to_xcvr[3:0]
reconfig_from_xcvr[/4)17-1:0]
reconfig_to_xcvr[(70-1):0]
reconfig_from_xcvr[(46-1):0]
rx_block_lock
rx_hi_ber
rx_recovered_clk[]
rx_latency_adj[15:0]
tx_latency_adj[15:0]
pll_ref_clk
Transceiver
Serial Data SDR XGMII TX
Inputs from MAC
SDR XGMII RX
Outputs from PCS
towards MAC
Avalon-MM PHY
Management
Interface
Status, 1588
and Reference`
Clock
pll_powerdown
tx_digitalreset [-1:0]
tx_analogreset [-1:0]
tx_cal_busy [-1:0]
rx_digitalreset [-1:0]
rx_analogreset [-1:0]
rx_cal_busy [-1:0]
Reset Control
and Status
(Optional)
Note: The block diagram shown in the GUI labels the external pins with the interface type and places the
interface name inside the box. The interface type and name are used in the Hardware Component
Description File (_hw.tcl). If you turn on Show signals, the block diagram displays all top-level
signal names.
For more information about _hw.tcl files refer to refer to the Component Interface Tcl Reference chapter
in volume 1 of the Quartus II Handbook.
Related Information
Component Interface Tcl Reference
10GBASE-R PHY Data Interfaces
This section describes the 10GBASE-R PHY data interfaces.
The TX signals are driven from the MAC to the PCS. The RX signals are driven from the PCS to the
MAC.
Table 3-10: SDR XGMII TX Inputs
Signal Name Direction Description
XGMII TX Interface
3-14 10GBASE-R PHY Data Interfaces
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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