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Altera Transceiver PHY IP Core User Manual

Page 590

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Transceiver PLL IP Core for Stratix V, Arria V,

and Arria V GZ Devices

18

2015.01.19

UG-01080

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When a fractional PLL functions as the TX PLL, you must configure the Native PHY IP Core to use

external PLLs. If you also want to use CMU or ATX PLLs, you must use the device-specific Transceiver

PLL to instantiate them.
The MegaCore Library includes the following IP cores to instantiate external CMU and ATX PLLs:
• Stratix V Transceiver PLL

• Arria V Transceiver PLL

• Arria V GZ Transceiver PLL
You instantiate the Altera Phase-Locked Loop (ALTERA_ PLL) IP Core to specify the fractional PLL and

the Native PHY IP Core to specify the PMA and PCS settings. In the Native PHY GUI, select the Use

external TX PLL option under the TX PLL Options heading. When you choose this option, the Native

PHY includes a top-level bus,

ext_pll_clk[

-1:0]

that you can connect to the external CMU, ATX,

and fractional PLLs. To achieve different TX channel data rates, you create point-to-point connections

between

ext_pll_clk[

-1:0]

and the CMU, ATX, and fractional PLLs required.

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