Altera Transceiver PHY IP Core User Manual
Page 694
Date
Document
Version
Changes Made
Interlaken Transceiver PHY
November 2011
1.3
• Added
tx_sync_done
signal which indicates that all lanes of TX
data are synchronized.
•
tx_coreclk_in
is required in this release.
• Added base data rate, lane rate, input clock frequency, and
PLL type parameters.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
PHY IP Core for PCI Express (PIPE)
November 2011
1.3
• Added
pll_powerdown
bit (bit[0] of 0x044) for manual reset
control. You must assert this bit for 1 ms for Gen2 operation.
• Added PLL type and base data rate parameters.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
Custom Transceiver PHY
November 2011
1.3
• Added Arria V and Cyclone V support.
• Addedbase data rate, lane rate, input clock frequency, and PLL
type parameters.
• Revised reset options. The 2 options for reset are now the
embedded reset controller or a user-specified reset logic.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
Low Latency PHY
November 2011
1.3
• Added base data rate, lane rate, input clock frequency, and PLL
type parameters.
• Updated QSF settings to include text strings used to assign
values and location of the assignment which is either a pin or
PLL.
• Revised reset options. The 2 options for reset are now the
embedded reset controller or a user-specified reset logic.
Deterministic Latency
November 2011
1.3
• Initial release.
Transceiver Reconfiguration Controller
21-34
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core