Altera Transceiver PHY IP Core - Manual (Page 207)

Word Addr Bits R/W Register Name Description
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to
lock to the incoming data. Bit <n>
corresponds to channel <n>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to
lock to the reference clock. Bit <n>
corresponds to channel <n>.
0x066 [31:0] R
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR
PLL is locked to the RX data, and that the
RX CDR has changed from LTR to LTD
mode. Bit <n> corresponds to channel <n>.
0x067 [31:0] R
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR
PLL is locked to the reference clock. Bit <n>
corresponds to channel <n>.
PCS for PCI Express
0x080 [31:0] RW
Lane or group number
Specifies lane or group number for indirect
addressing, which is used for all PCS
control and status registers. For variants
that stripe data across multiple lanes, this is
the logical group number. For non-bonded
applications, this is the logical lane number.
0x081
[31:6] R Reserved —
[5:1] R
rx_bitslipboundaryselectout Records the number of bits slipped by the
RX Word Aligner to achieve word
alignment. Used for very latency sensitive
protocols.
From block: Word aligner.
[0] R
rx_phase_comp_fifo_error When set, indicates an RX phase compensa‐
tion FIFO error.
From block: RX phase compensation FIFO.
0x082
[31:1] R Reserved —
[0] RW
tx_phase_comp_fifo_error When set, indicates a TX phase compensa‐
tion FIFO error.
From block: TX phase compensation FIFO.
UG-01080
2015.01.19
PHY for PCIe (PIPE) Register Interface and Register Descriptions 8-19
PHY IP Core for PCI Express (PIPE) Altera Corporation
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