Altera Transceiver PHY IP Core - Manual (Page 103)

Word
Addr
Bit R/W Name Description
20:16 RW
LT VPOST ovrd
Override value for the VPOSTRULE parameter. When
enabled, this value substitutes for the VPOSTRULE to allow
channel-by-channel override of the device settings. This
override only effects the local device TX output for this
channel.
The value to be substituted must be greater than the
INITPOSTVAL parameter for proper operation.
21 RW
LT VPOST ovrd
Enable
When set to 1, enables the override value for the
VPOSTRULE parameter stored in the
LT VPOST ovrd
register field.
27:24 RW
LT VPre ovrd
Override value for the VPRERULE parameter. When
enabled, this value substitutes for the VPOSTRULE to allow
channel-by-channel override of the device settings. This
override only effects the local device TX output for this
channel.
The value greater than the INITPREVAL parameter for
proper operation.
28 RW
LT VPre ovrd
Enable
When set to 1, enables the override value for the VPRERULE
parameter stored in the
LT VPre ovrd
register field.
PMA Registers
The PMA registers allow you to reset the PMA and provide status information.
Table 4-20: PMA Registers - Reset and Status
The following PMA registers allow you to reset the PMA and provide status information.
Addr Bit Access Name Description
0x22 0 RO
pma_tx_pll_is_
locked
Indicates that the TX PLL is locked to the input
reference clock.
0x44
1 RW
reset_tx_
digital
Writing a 1 causes the internal TX digital reset signal
to be asserted. You must write a 0 to clear the reset
condition.
2 RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal
to be asserted. You must write a 0 to clear the reset
condition.
3 RW
reset_rx_
digital
Writing a 1 causes the internal RX digital reset signal
to be asserted. You must write a 0 to clear the reset
condition.
0x61 [31:0] RW
phy_serial_
loopback
Writing a 1 puts the channel in serial loopback mode.
UG-01080
2015.01.19
PMA Registers 4-47
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Altera Corporation
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