Altera Transceiver PHY IP Core - Manual (Page 261)

Table 10-7: Avalon-ST interface
Signal Name Direction Description
tx_parallel_data[-1:0]
Input This is TX parallel data driven from the
MAC FPGA fabric. The ready latency on
this interface is 0, so that the PCS in Low-
Latency Bypass Mode or the MAC in PMA
Direct mode must be able to accept data as
soon as it comes out of reset.
tx_clkout[-1:0]
Output This is the clock for TX parallel data.
tx_ready[-1:0]
Output When asserted, indicates that the Low
Latency IP Core has exited the reset state is
ready to receive data from the MAC. This
signal is available if you select Enable
embedded reset control on the Additional
Options tab.
rx_parallel_data [ -1:0]
Output This is RX parallel data driven by the Low
Latency PHY IP Core. Data driven from
this interface is always valid.
rx_clkout[<n>-1:0]
Output Low speed clock recovered from the serial
data.
rx_ready[>-1:0]
Output This is the ready signal for the RX interface.
The ready latency on this interface is 0, so
that the MAC must be able to accept data
as soon as the PMA comes out of reset.
This signal is available if you select Enable
embedded reset control on the Additional
Options tab.
The following table describes the signals that comprise the serial data interface:
Table 10-8: Serial Data Interface
Signal Name Direction Description
rx_serial_data[-1:0]
Input Differential high speed input serial data.
tx_serial_data [-1:0]
Output Differential high speed output serial data.
10-14 Low Latency PHY Data Interfaces
UG-01080
2015.01.19
Altera Corporation Low Latency PHY IP Core
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