Altera Transceiver PHY IP Core - Manual (Page 506)

Figure 15-3: Common Interface Ports
tx_pll_refclk[-1:0]
tx_pma_clkout[-1:0]
rx_pma_clkout[-1:0]
rx_cdr_refclk[-1:0]
Clock Input
& Output Signals
rx_seriallpbken[-1:0]
rx_setlocktodata[-1:0]
rx_setlocktoref[-1:0]
pll_locked[
-1:0]
rx_is_lockedtodata[-1:0]
rx_is_lockedtoref[-1:0]
rx_clkslip[-1:0]
Control &
Status Ports pll_powerdown[
-1:0]
tx_analogreset[-1:0]
tx_digitalreset[-1:0]
rx_analogreset[-1:0]
rx_digitalreset[-1:0]
Resets
tx_parallel_data[44-1:0]
rx_parallel_data[64-1:0]
Parallel
Data Ports
tx_serial_data[-1:0]
rx_serial_data[-1:0]
TX & RX
Serial Ports
reconfig_to_xcvr [(70-1):0]
reconfig_from_xcvr [(46-1):0]
tx_cal_busy[-1:0]
rx_cal_busy[-1:0]
Reconfiguration
Interface Ports
Native PHY Common Interfaces
ext_pll_clk[
-1:0]
Table 15-16: Native PHY Common Interfaces
Name Direction Description
Clock Inputs and Output Signals
tx_pll_refclk[-1:0] Input The reference clock input to the TX PLL.
rx_pma_clkout[-1:0] Output RX parallel clock (recovered clock)
output from PMA
rx_cdr_refclk[-1:0] Input Input reference clock for the RX PFD
circuit.
ext_pll_clk[
-1:0]
Input This optional signal is created when you
select the Use external TX PLL option. If
you instantiate a fractional PLL which is
external to the Native PHY IP, then
connect the output clock of this PLL to
ext_pll_clk
.
Resets
UG-01080
2015.01.19
Common Interface Ports 15-23
Cyclone V Transceiver Native PHY IP Core Overview Altera Corporation
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