Altera Transceiver PHY IP Core - Manual (Page 3)

Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC
Option..............................................................................................................4-1
10GBASE-KR PHY Release Information................................................................................................. 4-3
Device Family Support................................................................................................................................4-3
10GBASE-KR PHY Performance and Resource Utilization..................................................................4-3
Parameterizing the 10GBASE-KR PHY....................................................................................................4-4
10GBASE-KR Link Training Parameters .................................................................................... 4-5
10GBASE-KR Auto-Negotiation and Link Training Parameters............................................. 4-7
10GBASE-R Parameters..................................................................................................................4-7
1GbE Parameters..............................................................................................................................4-9
Speed Detection Parameters.........................................................................................................4-10
PHY Analog Parameters............................................................................................................... 4-10
10GBASE-KR PHY IP Core Functional Description........................................................................... 4-10
10GBASE-KR PHY Arbitration Logic Requirements...........................................................................4-14
10GBASE-KR PHY State Machine Logic Requirements......................................................................4-15
Forward Error Correction (Clause 74)................................................................................................... 4-15
10BASE-KR PHY Interfaces.....................................................................................................................4-19
10GBASE-KR PHY Clock and Reset Interfaces.................................................................................... 4-20
10GBASE-KR PHY Data Interfaces............................................................................................ 4-22
10GBASE-KR PHY Control and Status Interfaces....................................................................4-25
Daisy-Chain Interface Signals......................................................................................................4-27
Embedded Processor Interface Signals....................................................................................... 4-28
Dynamic Reconfiguration Interface Signals.............................................................................. 4-29
Register Interface Signals..........................................................................................................................4-32
10GBASE-KR PHY Register Definitions................................................................................................4-32
PMA Registers............................................................................................................................................4-47
PCS Registers..............................................................................................................................................4-48
Creating a 10GBASE-KR Design.............................................................................................................4-49
Editing a 10GBASE-KR MIF File ........................................................................................................... 4-50
Design Example..........................................................................................................................................4-52
SDC Timing Constraints.......................................................................................................................... 4-53
Acronyms....................................................................................................................................................4-53
1G/10 Gbps Ethernet PHY IP Core.....................................................................5-1
1G/10GbE PHY Release Information....................................................................................................... 5-2
Device Family Support................................................................................................................................5-3
1G/10 GbE PHY Performance and Resource Utilization.......................................................................5-3
Parameterizing the 1G/10GbE PHY..........................................................................................................5-4
1GbE Parameters..........................................................................................................................................5-4
Speed Detection Parameters.......................................................................................................................5-5
PHY Analog Parameters............................................................................................................................. 5-6
1G/10GbE PHY Interfaces..........................................................................................................................5-7
1G/10GbE PHY Clock and Reset Interfaces............................................................................................ 5-8
1G/10GbE PHY Data Interfaces................................................................................................................ 5-9
XGMII Mapping to Standard SDR XGMII Data.................................................................................. 5-11
Serial Data Interface.................................................................................................................................. 5-12
Altera Transceiver PHY IP Core User Guide TOC-3
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