Altera Transceiver PHY IP Core User Manual
Page 537
as a diagnostic tool to perform in-system link analysis without interrupting the link traffic. The steps
below provide BERB operation example:
• Write 3'b111 to bit[2:0] in offset 0x0 to enable BERB
• Set Horizontal Phase and/or Vertical High in offset 0x1 and/or 0x2
• Set 2'b01 to bit[4:3] in offset 0x0 to reset the counters
• Set 2'b10 to bit [4:3] in offset 0x0 to take a snapshot of the counters. Read the counter values from
offsets 0x5 to 0x8.
• Repeat steps 2 to 4 to measure the bit error rate (BER) for another horizontal phase / veritical height.
Transceiver Reconfiguration Controller DFE Registers
The DFE is an infinite impulse response filter (non-linear) that compensates for inter-symbol interference
(ISI). Because the values of symbols previously detected are known, the DFE engine can estimate the ISI
contributed by these symbols and cancel out this ISI by subtracting the predicted value from subsequent
symbols.
This mechanism allows DFE to boost the signal to noise ratio of the received data. You can use DFE in
conjunction with the receiver's linear equalization and with the transmitter's pre-emphasis feature. DFE is
only available for Stratix V devices.
DFE automatically runs offset calibration and phase interpolator (PI) phase calibration on all channels
after power up. You can run DFE manually to determine the optimal settings by monitoring the BER of
the received data at each setting and specify the DFE settings that yield the widest eye.
Note: If you are using the EyeQ monitor with DFE enabled, you must put the EyeQ monitor in 1D mode
by writing the EyeQ 1D-eye bit. For more information, refer to EyeQ Offsets and Values.
Note: If you are using a PHY IP that has DFE enabled with a reconfiguration controller and/or if you are
using ATX PLLs in your design, then the reference clock to the PHY IP must be stable before the
reconfiguration controller is taken out of reset state.
The following table lists the direct DFE registers that you can access using Avalon-MM reads and writes
on reconfiguration management interface.
Note: All undefined register bits are reserved.
Table 16-13: DFE Registers
Reconfig Addr
Bits
R/W
Register Name
Description
7’h18
[9:0] RW
logical channel address
The logical channel address. Must be
specified when performing dynamic
updates. The Transceiver Reconfiguration
Controller maps the logical address to the
physical address.
16-20
Transceiver Reconfiguration Controller DFE Registers
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview