Altera Transceiver PHY IP Core - Manual (Page 329)

Table 12-24: 10G TX FIFO Parameters
Parameter Range Description
TX FIFO Mode
Interlaken
phase_comp
register
Specifies one of the following 3 modes:
• interlaken : The TX FIFO acts as an
elastic buffer. The FIFO write clock
frequency (
coreclk
) can exceed that
of the effective read clock,
tx_
clkout
. You can control writes to
the FIFO with
tx_data_valid
. By
monitoring the FIFO flags, you can
avoid the FIFO full and empty
conditions. The Interlaken frame
generator controls reads.
• phase_comp : The TX FIFO
compensates for the clock phase
difference between the
coreclkin
and
tx_clkout
which is an internal
PCS clock.
• register : The TX FIFO is bypassed.
tx_data
and
tx_data_valid
are
registered at the FIFO output. You
must control
tx_data_valid
precisely based on gearbox ratio to
avoid gearbox underflow or overflow
conditions.
TX FIFO full threshold
0-31
Specifies the full threshold for the 10G
PCS TX FIFO. The active high TX FIFO
full flag is synchronous to
coreclk
. The
default value is 31.
TX FIFO empty threshold
0-31
Specifies the empty threshold for the
10G PCS TX FIFO. The active high TX
FIFO empty flag is synchronous to
coreclk
. The default value is 0.
TX FIFO partially full threshold
0-31
Specifies the partially full threshold for
the 10G PCS TX FIFO. The active high
TX FIFO partially full flag is synchro‐
nous to
coreclk
. The default value is 23.
TX FIFO partially empty threshold
0-31
Specifies the partially empty threshold
for the 10G PCS TX FIFO. The active
high TX FIFO partially empty flag is
synchronous to
coreclk
.
Enable tx_10g_fifo_full port On/Off When you turn this option On , the 10G
PCS includes the active high
tx_10g_
fifo_full
port.
tx_10g_fifo_full
is
synchronous to
coreclk
.
UG-01080
2015.01.19
10G PCS Parameters for Stratix V Native PHY 12-31
Stratix V Transceiver Native PHY IP Core Altera Corporation
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