Altera Transceiver PHY IP Core User Manual
Page 680
Date
Document
Version
Changes Made
March 2013
2.0
Initial Release.
Analog Parameters Set Using QSF Assignment
March 2013
2.0
Made the following changes.
• Changed choices for
XCVR_RX_SD_ENABLE
from TRUE/FALSE
to On/Off
• Corrected definitions of
XCVR_IO_PIN_TERMINATION
and
XCVR_
GT_IO_PIN_TERMINATION
which were reversed.
• Added references to Knowledge Base Solution showing the
mapping of Transceiver Toolkit settings to
XCVR_TX_PRE_EMP_
PRE_TAP
,
XCVR_TX_PRE_EMP_INV_PRE_TAP
and
XCVR_TX_PRE_
EMP_PRE_TAP_USER
for Arria V GZ and Stratix V devices.
• Added references to Knowledge Base Solution showing the
mapping of Transceiver Toolkit settings to
XCVR_TX_PRE_EMP_
2ND_POST_TAP
,
XCVR_TX_PRE_EMP_INV_2ND_TAP
, and
XCVR_TX_
PRE_EMP_2ND_POST_TAP_USER
for Arria V GZ and Stratix V
devices.
Migrating from Stratix IV to Stratix V Devices
March 2013
2.0
No changes from previous release.
Date
Document
Version
Changes Made
Introduction and Getting Started
February 2013
1.9
• Reformatted.
10GBASE-R PHY
February 2013
1.9
• Reformatted.
• Corrected definition of the PLL type parameter. Altera
recommends the ATX PLL for data rates greater than 8 Gbps.
Backplane Ethernet 10GBASE-KR PHY
February 2013
1.9
• Reformatted.
• Removed description of PMA
reset_ch_bitmask
at 0x41 which
is not available. Added definition of digital and analog resets at
0x44, bits 1-3.
• Removed definitions of
trn_in_trigger
and
trn_out_
trigger
buses which are not used.
• Corrected direction of
xgmii_rx_clk
in pinout figure.
1G/10GbE PHY
21-20
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core