Altera Transceiver PHY IP Core - Manual (Page 30)

Table 3-2: Latency for TX and RX PCS and PMA Stratix V Devices
PCS (Parallel Clock Cycles)
PMA (UI) 32-bit PMA Width 40-bit PMA Width
Minimum Maximum Minimum Maximum
TX 7 12 8 12 124
RX 14 33 15 34 43
Related Information
• IEEE 802.3 Clause 49
• 10-Gbps Ethernet MAC MegaCore Function User Guide
• Transceiver Configurations in Stratix V Devices
10GBASE-R PHY Release Information
Release information for the IP core.
Table 3-3: 10GBASE-R Release Information
Item Description
Version 13.1
Release Date November 2013
Ordering Codes (3) IP-10GBASERPCS (primary) IPR-10GBASERPCS
(renewal)
Product ID 00D7
Vendor ID 6AF7
10GBASE-R PHY Device Family Support
Device support for the IP core.
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 3-4: Device Family Support
Device Family Support
Arria V GT devices–Soft PCS and Hard PMA Final
(3) No ordering codes or license files are required for Stratix V devices.
3-6 10GBASE-R PHY Release Information
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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