Altera Transceiver PHY IP Core - Manual (Page 290)

Signal Name Direction Description
rx_cal_busy [-1:0]
Output When asserted, indicates that the
initial RX calibration is in progress. It
is also asserted if reconfiguration
controller is reset. It will not be
asserted if you manually re-trigger
the calibration IP.
Related Information
• Transceiver Reset Control in Arria V Devices
• Transceiver Reset Control in Cyclone V Devices
• Transceiver Reset Control in Stratix V Devices
Register Interface and Descriptions for Deterministic Latency PHY
Describes the register interface and descriptions for the Deterministic Latency PHY IP core.
The Avalon-MM PHY management interface provides access to the Deterministic Latency PHY PCS and
PMA registers that control the TX and RX channels, the PMA powerdown and PLL registers, and
loopback modes.
The following figure illustrates the role of the PHY Management module in the Deterministic Latency
PHY.
11-22 Register Interface and Descriptions for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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