Option -1 – Altera Transceiver PHY IP Core User Manual
Page 57
Backplane Ethernet 10GBASE-KR PHY IP Core
with Early Access FEC Option
4
2015.01.19
UG-01080
The Backplane Ethernet 10GBASE-KR PHY MegaCore
®
function is available for Stratix
®
V and Arria V
GZ devices.
This transceiver PHY allows you to instantiate both the hard Standard PCS and the higher performance
hard 10G PCS and hard PMA for a single Backplane Ethernet channel. It implements the functionality
described in the IEEE Std 802.3ap-2007 Standard. Because each instance of the 10GBASE-KR PHY IP
Core supports a single channel, you can create multi-channel designs by instantiating more than one
instance of the core. The following figure shows the 10GBASE-KR transceiver PHY and additional blocks
that are required to implement this core in your design.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html
. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134