Altera Transceiver PHY IP Core User Manual
Page 157
neous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include the
required signal in the top-level module of your XAUI PHY IP Core.
Table 6-13: Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices
Name
Direction
Description
rx_invpolarity[3:0]
Input
Dynamically reverse the polarity of every bit of the RX
data at the input of the word aligner.
rx_set_locktodata[3:0]
Input
Force the CDR circuitry to lock to the received data.
rx_is_lockedtodata[3:0]
Output
When asserted, indicates the RX channel is locked to
input data.
rx_set_locktoref[3:0]
Input
Force the receiver CDR to lock to the phase and
frequency of the input reference clock.
rx_is_lockedtoref[3:0]
Output
When asserted, indicates the RX channel is locked to
input reference clock.
tx_invpolarity[3:0]
Input
Dynamically reverse the polarity the data word input to
the serializer in the TX datapath.
rx_seriallpbken
Input
Serial loopback enable.
• 1: Enables serial loopback
• 0: Disables serial loopback
This signal is asynchronous to the receiver. The status of
the serial loopback option is recorded by the PMA
channel controller, word address 0x061.
rx_channelaligned
Output
When asserted indicates that the RX channel is aligned.
pll_locked
Output
In LTR mode, indicates that the receiver CDR has locked
to the phase and frequency of the input reference clock.
rx_rmfifoempty[3:0]
Output
Status flag that indicates the rate match FIFO block is
empty (5 words). This signal remains high as long as the
FIFO is empty and is asynchronous to the RX datapath.
rx_rmfifofull[3:0]
Output
Status flag that indicates the rate match FIFO block is full
(20 words). This signal remains high as long as the FIFO
is full and is asynchronous to the RX data.
rx_disperr[7:0]
Output
Received 10-bit code or data group has a disparity error.
It is paired with
rx_errdetect
which is also asserted
when a disparity error occurs. The
rx_disperr
signal is 2
bits wide per channel for a total of 8 bits per XAUI link.
UG-01080
2015.01.19
XAUI PHY Optional PMA Control and Status Interface
6-17
XAUI PHY IP Core
Altera Corporation