Altera Transceiver PHY IP Core User Manual
Page 204
Figure 8-5: PCI Express PIPE IP Core Top-Level Modules
System
Interconnect
Fabric
to Embedded
Controller
to
Reconfiguration
Controller
Clocks
Tx Data, Datak
PIPE Control
PHY IP Core for PCI Express
Hard PCS and PMA
PHY IP Core for PCI Express and Avalon-MM Control Interface for Non-PIPE Functionality
Dynamic
Reconfiguration
PIPE Control
Tx Data, Datak
Clocks
PIPE Status
Rx Data, Datak
Valid
Clocks
Reset
Non-PIPE
Status
Non-PIPE
Control
S
Avalon-MM
Control
Non-PIPE
S
Avalon-MM
Status
Non-PIPE
Reset
Controller
PIPE reset
M
Avalon-MM
PHY
Mgmt
S
Table 8-10: Avalon-MM PHY Management Interface
Signal Name
Direction
Description
phy_mgmt_clk
Input
Avalon-MM clock input.
There is no frequency restriction for Stratix V devices;
however, if you plan to use the same clock for the PHY
management interface and transceiver reconfiguration,
you must restrict the frequency range of
phy_mgmt_clk
to 100-125 MHz to meet the specification for the
transceiver reconfiguration clock.
phy_mgmt_clk_reset
Input
Global reset signal that resets the entire PHY IP core.
This signal is active high and level sensitive.
phy_mgmt_address[8:0]
Input
9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input
Input data.
phy_mgmt_readdata[31:0]
Output
Output data.
8-16
PHY for PCIe (PIPE) Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation
PHY IP Core for PCI Express (PIPE)