Deterministic latency phy ip core, Deterministic latency phy ip core -1 – Altera Transceiver PHY IP Core User Manual
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Deterministic Latency PHY IP Core
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2015.01.19
UG-01080
Deterministic latency enables accurate delay measurements and known timing for the transmit (TX) and
receive (RX) datapaths as required in applications such as wireless communication systems, emerging
Ethernet standards, and test and measurement equipment. The Deterministic Latency PHY IP Core
support 1-32 lanes with a continuous range of data rates from 611–6144 Mbps for Arria V devices,
0.6222–6.144 Gbps in Arria V GZ, 611–5000 Mbps in Cyclone V devices, and 611 Mbps–12200 Mbps for
Stratix V devices. By setting the appropriate options using the MegaWizard Plug-In Manager, you can
configure the Deterministic Latency PHY IP Core to support many industry-standard protocols that
require deterministic latency, including the following protocols:
• Common Public Radio Interface (CPRI)
• Open Base Station Architecture Initiative (OBSAI)
• 1588 Ethernet
For more information about using the Deterministic Latency PHY IP Core to implement CPRI, refer to
the application note, Implementing the CPRI Protocol Using the Deterministic PHY IP Core.
The following figure illustrates the top-level interfaces and modules of the Deterministic Latency PHY IP
Core. As the figure shows, the physical coding sublayer (PCS) includes the following functions:
• TX and RX Phase Compensation FIFO
• Byte serializer and deserializer
• 8B/10B encoder and decoder
• Word aligner
• TX bit slipper
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